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k4x51323pc - 7(8)e/g march 2006 1 mobile-ddr sdram 16m x32 mobile-ddr sdram features ? 1.8v power supply, 1.8v i/o power ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? four banks operation ? 1 /cs ? 1 cke ? differential clock inputs(ck and ck ) ? mrs cycle with address key programs - cas latency ( 2, 3 ) - burst length ( 2, 4, 8, 16 ) - burst type (sequential & interleave) - partial self refresh type ( full, 1/2, 1/4 array ) - output driver strength control ( full, 1/2, 1/4, 1/8 ) ? internal temperature compensated self refresh ? deep power down mode ? all inputs except data & dm are sampled at the positive going edge of the system clock(ck). ? data i/o transactions on both edges of data strobe, dm for masking. ? edge aligned data output, center aligned data input. ? no dll; ck to dqs is not synchronized. ? dm0 - dm3 for write masking only. ? auto refresh duty cycle - 7.8us for -25 to 85 c address configuration - dm is internally loaded to match dq and dqs identically. organization bank row column 16m x32 ba0,ba1 a0 - a12 a0 - a8 operating frequency note : 1. cas latency ddr266 ddr222 speed @cl2 *1 83mhz 66mhz speed @cl3 *1 133mhz 111mhz ordering information - 7(8)e : 90fbga pb(pb free), normal power, extended temperature(-25 c ~ 85 c) - 7(8)g : 90fbga pb(pb free), low power, extended temperature(-25 c ~ 85 c) - c3/ca : 133mhz(cl=3) / 111mhz(cl=3) part no. max freq. interface package k4x51323pc-7(8)e/gc3 133mhz(cl=3),83mhz(cl=2) lvcmos 90fbga pb (pb free) k4x51323pc-7(8)e/gca 111mhz(cl=3),66mhz(cl=2) information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is pro- vided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any mi litary or defense application, or any governmental procurement to which special terms or pro- visions may apply.
k4x51323pc - 7(8)e/g march 2006 2 mobile-ddr sdram bank select timing register dm input register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 2mx64 2mx64 2mx64 2mx64 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck, ck add lcke ck, ck cke cs ras cas we lcas lras lcbr lwe lwcbr lras lcbr ck, ck 64 64 32 32 ldm x32 dqi data strobe functional block diagram dm ldm lwe
k4x51323pc - 7(8)e/g march 2006 3 mobile-ddr sdram 90ball(6x15) fbga 123789 av ss dq31 v ssq v ddq dq16 vdd bv ddq dq29 dq30 dq17 dq18 v ssq cv ssq dq27 dq28 dq19 dq20 v ddq dv ddq dq25 dq26 dq21 dq22 v ssq ev ssq dqs3 dq24 dq23 dqs2 v ddq fv dd dm3 nc nc dm2 v ss gcke ck ck we cas ras h a9 a11 a12 cs ba0 ba1 ja6a7a8a10a0a1 k a4 dm1 a5 a2 dm0 a3 lv ssq dqs1 dq8 dq7 dqs0 v ddq mv ddq dq9dq10dq5 dq6 v ssq nv ssq dq11 dq12 dq3 dq4 v ddq pv ddq dq13 dq14 dq1 dq2 v ssq rv ss dq15 v ssq v ddq dq0 v dd package dimension and pin configuration < bottom view *1 > < top view *2 > symbol min typ max a- -1.00 a 1 0.25 - - e 10.9 11.0 11.1 e 1 -6.40- d 12.9 13.0 13.1 d 1 -11.2- e - 0.80 - b 0.45 0.50 0.55 z--0.10 [unit::mm] 521 63 4 8 97 f e d c b j h g a e d d 1 e 1 e #a1 ball origin indicator m l k r p n k4x51323pc-xxxx samsung week ball name ball function ck, ck system differential clock cs chip select cke clock enable a0 ~ a12 address ba0 ~ ba1 bank select address ras row address strobe cas column address strobe we write enable dm0~3 data input mask dqs0~3 data strobe dq0 ~ 31 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground z a a1 b < top view *1 >
k4x51323pc - 7(8)e/g march 2006 4 mobile-ddr sdram input/output function description symbol type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . internal clock signals are derived from ck/ck . cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any banks). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. cs input chip select : cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. dm0,dm1, dm2,dm3 input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to match the dq and dqs loading. for the x32, dm0 corresponds to the data on dq0-dq7 ; dm1 corresponds to the data on dq8-dq15, dm2 corresponds to the data on dq16-dq23, dm3 corresponds to the data on dq24-dq31 ba0, ba1 input bank addres inputs : ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. a [n : 0] input address inputs : provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. ba0 and ba1 determines which mode register ( mode register or extended mode register ) is loaded during the mode register set command. dq i/o data input/output : data bus dqs0,dqs1, dqs2,dqs3 i/o data strobe : output with read data, input with write data. edge-aligned with read data, centered in write data. it is used to fetch write data. for the x3 2, dqs0 corresponds to the data on dq0-dq7 ; dqs1 corresponds to the data on dq8-dq15,dqs2 corresponds to the data on dq16-dq23, dqs3 corre- sponds to the data on dq24-dq31 nc - no connect : no internal electrical connection is present. vddq supply dq power supply : 1.7v to 1.95v vssq supply dq ground. vdd supply power supply : 1.7v to 1.95v vss supply ground.
k4x51323pc - 7(8)e/g march 2006 5 mobile-ddr sdram functional description figure.1 state diagram read self refresh auto refresh power down row active reada writea writea precharge preall idle power down refs refsx refa mrs ckel ckeh act ckeh ckel write write writea reada pre pre reada reada read read automatic sequence command sequence writea burst stop self refresh partial pre deep power down ckeh deep mrs emrs all banks precharge on power power applied power down all banks precharged pre
k4x51323pc - 7(8)e/g march 2006 6 mobile-ddr sdram mode register definition mode register set(mrs) address bus a 2 a 1 a 0 burst length 0 0 0 reserved 001 2 010 4 011 8 100 16 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved a 3 burst type 0 sequential 1 interleave mode register ba1 ba0 a12 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 bt burst length 0 figure.2 mode register set the mode register is designed to support the various operating modes of ddr sdram. it includes cas latency, addressing mode, burst length, test mode and vendor specific options to make d dr sdram useful for variety of applications. the default value of the mode register is not defined, therefore the mode register must be written in the power up sequence of ddr sdram. the mode reg- ister is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writing into the mode register). the states of address pins a0 ~ a12 and ba0, ba1 in the same cycle as cs , ras , cas and we going low are written in the mode register. two clock cycles are re quired to complete the write operation in the mode register. even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. this command mu st be issued only when all banks are in the idle state. if mode register is changed, extended mode register automatically is reset and come into default state. so extended mode register must be set again. the mode register is divided into various fields depending on functionality. the burst length uses a0 ~ a2, addressing mode uses a3, cas latency(read latency from column address) uses a4 ~ a6, a7 ~ a12 is used for test mode. ba0 and ba1 must be set to low for proper mrs operation. rfu* 0 0 0 cas latency a6 a5 a4 cas latency 000 reserved 001 reserved 010 2 011 3 100 reserved 101 reserved 110 reserved 111 reserved note : rfu(reserved for future use) should stay "0" during mrs cycle
k4x51323pc - 7(8)e/g march 2006 7 mobile-ddr sdram burst address ordering for burst length burst length starting address (a3, a2, a1, a0) sequential mode interleave mode 2 xxx0 0, 1 0, 1 xxx1 1, 0 1, 0 4 xx00 0, 1, 2, 3 0, 1, 2, 3 xx01 1, 2, 3, 0 1, 0, 3, 2 xx10 2, 3, 0, 1 2, 3, 0, 1 xx11 3, 0, 1, 2 3, 2, 1, 0 8 x000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 x001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 x010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 x011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 x100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 x101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 x110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 x111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 16 0000 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0001 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14 0010 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1 2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13 0011 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12 0100 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11 0101 5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10 0110 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9 0111 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8 1000 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7 8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7 1001 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8 9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6 1010 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5 1011 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4 1100 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3 1101 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12 13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2 1110 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 1111 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
k4x51323pc - 7(8)e/g march 2006 8 mobile-ddr sdram extended mode register set(emrs) the extended mode register is designed to support partial arra y self refresh or driver strength control. emrs cycle is not m andatory and the emrs command needs to be issued only when either pasr or ds is used. the default state without emrs command issued is half driver strength, and full array refreshed. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba1 ,low on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0 ~ a12 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. two clock cycles are required to comp lete the write operation in the extended mode register. even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be chang ed with the same command and two clock cycles. but this command must be issued only when all banks are in the idle state. a0 - a2 are used for partial array self refresh and a5 - a6 are used for driver strength control. "high" on ba1 and"low" on ba0 are u sed for emrs. all the other address pins except a0,a1,a2,a5,a6, ba1, ba0 must be set to low for proper emrs operation. refer to the table for specific codes. extended mrs for pasr(partial array self refresh) & ds(driver strength control) address bus ba1 ba0 a12 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 1 pasr 0 rfu* 0 0 0 rfu* ds ds a 6 a 5 driver strength 0 0 full 0 1 1/2 1 0 1/4 1 1 1/8 pasr a 2 a 1 a 0 refreshed area 0 0 0 full array 0 0 1 1/2 of full array 0 1 0 1/4 of full array 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved internal tcsr self refresh cycle is controlled automatically by internal tem- perature sensor and control cir- cuit according to the three temperature ranges ; 45 c and 85 c note : rfu(reserved for future use) should stay "0" during emrs cycle figure.3 extended mode register set
k4x51323pc - 7(8)e/g march 2006 9 mobile-ddr sdram note : 1. in order to save power consumption, mobile-ddr sdram includes pasr option. 2. mobile-ddr sdram supports three kinds of pasr in self refresh mode; full array, 1/2 array, 1/4 array. - full array - 1/2 array - 1/4 array partial self refresh area figure.4 emrs code and tcsr , pasr partial array self refresh (pasr) ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 internal temperature compensated self refresh (tcsr) note : 1. in order to save power consumption, mobile ddr sdram includes the internal temperature sensor and control units to control the self refresh cycle automatically accord ing to the three temperature ranges ; 45 c and 85 c. 2. if the emrs for external tcsr is issued by the controller, this emrs code for tcsr is ignored. 3. it has +/- 5 c tolerance. temperature range self refresh current (idd6) unit - e - g full array 1/2 array 1/4 array full array 1/2 array 1/4 array 45 c *3 300 270 255 250 220 205 ua 85 c 600 500 450 500 400 350
k4x51323pc - 7(8)e/g march 2006 10 mobile-ddr sdram dc operating conditions absolute maximum ratings note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 2.7 v voltage on v dd supply relative to v ss v dd -0.5 ~ 2.7 v voltage on v ddq supply relative to v ss v ddq -0.5 ~ 2.7 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma recommended operating conditions(voltage referenced to vss=0v, tc = -25 c to 85 c) note : 1. under all conditions, vddq must be less than or equal to vdd. 2. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulat ion. parameter symbol min max unit note supply voltage(for device with a nominal vdd of 1.8v) vdd 1.7 1.95 v 1 i/o supply voltage vddq 1.7 1.95 v 1 input logic high voltage vih(dc) 0.7 x vddq vddq+0.3 v 2 input logic low voltage vil(dc) -0.3 0.3 x vddq v 2 output logic high voltage voh(dc) 0.9 x vddq - v ioh = -0.1ma output logic low voltage vol(dc) - 0.1 x vddq v iol = 0.1ma input leakage current ii -2 2 ua output leakage current ioz -5 5 ua
k4x51323pc - 7(8)e/g march 2006 11 mobile-ddr sdram dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, tc = -25 to 85 c) parameter symbol test condition ddr266 ddr222 unit operating current (one bank active) idd0 trc = trcmin ; tck = tckmin ; cke is high; cs is high between valid commands; address inputs are switching; data bus inputs are stable 80 70 ma precharge standby current in power-down mode idd2p all banks idle, cke is low; cs is high, tck = t ckmin ; address and control inputs are switching; data bus inputs are stable 0.3 ma idd2ps all banks idle, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 0.3 precharge standby current in non power-down mode idd2n all banks idle, cke is high; cs is high, tck = t ckmin ;address and control inputs are switching; data bus inputs are stable 12 10 ma idd2ns all banks idle, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 8 7 active standby current in power-down mode idd3p one bank active, cke is low; cs is high, tck = tckmin ;address and control inputs are switching; data bus inputs are stable 6 ma idd3ps one bank active, cke is low; cs is high, ck = low, ck = high;address and control inputs are switching; data bus inputs are stable 3 active standby current in non power-down mode (one bank active) idd3n one bank active, cke is high; cs is high, tck = tckmin ;address and control inputs are switching; data bus inputs are stable 25 20 ma idd3ns one bank active, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 20 15 operating current (burst mode) idd4r one bank active; bl = 4; cl = 3; tck = tckmin ; continuous read bursts; i out = 0 ma address inputs are switching; 50% data change each burst transfer 125 105 ma idd4w one bank active; bl = 4; tck = tckmin ; continuous write bursts;address inputs are switching; 50% data change each burst transfer 100 90 refresh current idd5 trc = trfcmin ; tck = tckmin ; burst refresh; cke is high;address and control inputs are switching; data bus inputs are stable 150 135 ma self refresh current idd6 cke is low; tck = tckmin ; extended mode register set to all 0?s; address and control inputs are stable; data bus inputs are stable tcsr 45* 1 85 c -e full 300 600 ua 1/2 270 500 1/4 255 450 -g full 250 500 1/2 220 400 1/4 205 350 deep power down current idd8* 2 address and control inputs are stable; data bus inputs are stable 10 ua note : 1. it has +/- 5 c tolerance. 2. dpd(deep power down) function is an optional feature, and it will be enabled upon request. please contact samsung for more information. 3. idd specifications are tested after the device is properly intialized. 4. input slew rate is 1v/ns. 5. definitions for idd: low is defined as v in 0.1 * vddq ; high is defined as v in 0.9 * vddq ; stable is defined as inputs stable at a high or low level ; switching is defined as: - address and command: inputs changing between high and low once per two clock cycles ; - data bus inputs: dq changing between high and l ow once per clock cycle; dm and dqs are stable.
k4x51323pc - 7(8)e/g march 2006 12 mobile-ddr sdram ac operating conditions & timming specification note : 1. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulat ion. 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. parameter/condition symbol min max unit note input high (logic 1) voltage, all inputs vih(ac) 0.8 x vddq vddq+0.3 v 1 input low (logic 0) voltage, all inputs vil(ac) -0.3 0.2 x vddq v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.4 x vddq 0.6 x vddq v 2
k4x51323pc - 7(8)e/g march 2006 13 mobile-ddr sdram ac timming parameters & specifications parameter symbol ddr266 ddr222 unit note min max min max clock cycle time cl=2 tck 12.0 15.0 ns cl=3 7.5 9.0 row cycle time trc 67.5 81 ns row active time tras 45 70,000 54 70,000 ns ras to cas delay trcd 22.5 27 ns row precharge time trp 22.5 27 ns row active to row active delay trrd 15 15 ns write recovery time twr 15 15 ns last data in to active delay tdal 2tck+trp 2tck+trp - 2 last data in to read command tcdlr 1 1 tck col. address to col. address delay tccd 1 1 tck clock high level width tch 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 tck dq output data access time from ck/ ck cl=2 tac 2 8 2.5 8 ns 3 cl=3 2 6 2.5 6 dqs output data access time from ck/ck cl=2 tdqsck 2 8 2.5 8 ns cl=3 2 6 2.5 6 data strobe edge to ouput data edge tdqsq 0.6 0.7 ns read preamble cl=2 trpre 0.5 1.1 0.5 1.1 tck cl=3 0.9 1.1 0.9 1.1 read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 ns 4 dqs-in hold time twpreh 0.25 0.25 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 tck dqs falling edge to ck setup time tdss 0.2 0.2 tck dqs falling edge hold time from ck tdsh 0.2 0.2 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 tck address and control input setup time tis 1.3 1.5 ns 1 address and control input hold time tih 1.3 1.5 ns 1 address & control input pulse width tipw 2.6 3.0 1 dq & dm setup time to dqs tds 0.8 1.1 ns 5,6 dq & dm hold time to dqs tdh 0.8 1.1 ns 5,6 dq & dm input pulse width tdipw 1.8 2.4 ns dq & dqs low-impedence time from ck/ck tlz 1.0 1.0 ns dq & dqs high-impedence time from ck/ck thz 6.0 7.0 ns dqs write postamble time twpst 0.4 0.6 0.4 0.6 tck dqs write preamble time twpre 0.25 0.25 tck
k4x51323pc - 7(8)e/g march 2006 14 mobile-ddr sdram parameter symbol ddr266 ddr222 unit note min max min max refresh interval time tref 64 64 ms mode register set cycle time tmrd 2 2 tck power down exit time tpdex 1*tck +tis 1*tck +tis ns cke min. pulse width(high and low pulse width) tcke 2 2 tck auto refresh cycle time trfc 80 90 ns 7 exit self refresh to active command txsr 120 120 ns data hold from dqs to earliest dq edge tqh thpmin - tqhs thpmin - tqhs ns data hold skew factor tqhs 0.75 1.0 ns clock half period thp tclmin or tchmin tclmin or tchmin ns
k4x51323pc - 7(8)e/g march 2006 15 mobile-ddr sdram note : 1. input setup/hold slew rate derating this derating table is used to increase t is /t ih in the case where the input slew rate is below 1.0v/ns. 2. minimum 3clk of tdal(= twr + trp) is required because it need minimum 2clk for twr and minimum 1clk for trp. 3. tac(min) value is measured at the high vdd(1.95v) and cold temperature(-25 c). tac(max) value is measured at the low vdd(1.7v) and hot temperature(85 c). tac is measured in the device with half driver strength and under the ac output load condition (fig.7 in next page). 4. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were prev iously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 5. i/o setup/hold slew rate derating this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 1.0v/ns. 6. i/o delta rise/fall rate(1/slew-rate) derating this derating table is used to increase tds/tdh in the case where the dq and dqs slew rates differ. the delta rise/fall rat e is calculated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 1.0v/ns and slew rate 2 =0.8v/ns, then the delta r ise/fall rate =-0.25ns/v. 7. maximum burst refresh cycle : 8 input setup/hold slew rate ? tis ? tih (v/ns) (ps) (ps) 1.0 0 0 0.8 +50 +50 0.6 +100 +100 i/o setup/hold slew rate ? tds ? tdh (v/ns) (ps) (ps) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 delta rise/fall rate ? tds ? tdh (ns/v) (ps) (ps) 000 0.25 +50 +50 0.5 +100 +100
k4x51323pc - 7(8)e/g march 2006 16 mobile-ddr sdram ac operating test conditions (v dd = 1.7v to 1.95v, t c = -25 to 85 c) parameter value unit ac input levels (vih/vil) 0.8 x vddq / 0.2 x vddq v input timing measurement reference level 0.5 x vddq v input signal minimum slew rate 1.0 v/ns output timing measurement reference level 0.5 x vddq v output load condition see figure.7 1.8v 13.9k ? 10.6k ? output 20pf v oh (dc) = 0.9 x vddq , i oh = -0.1ma v ol (dc) = 0.1 x vddq , i ol = 0.1ma vtt=0.5 x v ddq 50 ? output 20pf z0=50 ? input/output capacitance (v dd =1.8 , v ddq =1.8v , t c = 25 c , f=1mhz) parameter symbol min max unit input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras ,cas , we ) cin1 1.5 3.0 pf input capacitance( ck, ck ) cin2 1.5 3.5 pf data & dqs input/output capacitance cout 2.0 4.5 pf input capacitance(dm) cin3 2.0 4.5 pf figure.6 dc output load circuit figure.7 ac output load circuit
k4x51323pc - 7(8)e/g march 2006 17 mobile-ddr sdram ac overshoot/undershoot specification for address & control pins parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vdd 3v-ns maximum undershoot area below vss 3v-ns overshoot area maximum amplitude v dd undershoot area maximum amplitude v ss volts (v) figure.8 ac overshoot and undershoot definition for address and control pins time (ns) ac overshoot/undershoot specification for clk, dq, dqs and dm pins parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vddq 3v-ns maximum undershoot area below vssq 3v-ns overshoot area maximum amplitude v ddq undershoot area maximum amplitude v ssq volts (v) figure.9 ac overshoot and undershoot definition for clk, dq, dqs and dm pins time (ns)
k4x51323pc - 7(8)e/g march 2006 18 mobile-ddr sdram command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a12,a11, a9 ~ a0 note register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv lcolumn address (a0~a8) 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv lcolumn address (a0~a8) 4 auto precharge enable h 4, 6 deep power down entry h l l h h l x exit l h h x x x burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv vv exit l h x x x x precharge power down entry h l hx x x x lh hh exit l h hx x x lv vv dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 note : 1. op code : operand code. a0 ~ a12 & ba0 ~ ba1 : program keys. (@emrs/mrs) 2.emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba1 : bank select addresses. 5. if a10/ap is "high" at row precharge, ba0 and ba1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any functi on, which means "no operation(nop)" in ddr sdram.
k4x51323pc - 7(8)e/g march 2006 19 mobile-ddr sdram functional truth table current state cs ras cas we address command action precharge standby l h h l x burst stop illegal *2 l h l x ba, ca, a10 read/write illegal *2 l l h h ba, ra active bank active, latch ra l l h l ba, a10 pre/prea illegal *4 lllhx refresh auto-refresh *5 l l l l op-code, mode-add mrs mode register set *5 active standby l h h l x burst stop nop l h l h ba, ca, a10 read/reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write/writea begin write, latch ca, determine auto-precharge l l h h ba, ra active bank active/illegal *2 llhl ba, a10 pre/prea precharge/precharge all l l l h x refresh illegal l l l l op-code, mode-add mrs illegal read l h h l x burst stop terminate burst l h l h ba, ca, a10 read/reada terminate burst, latch ca, begin new read, determine auto-precharge *3 l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active bank active/illegal *2 l l h l ba, a10 pre/prea terminate burst, precharge l l l h x refresh illegal l l l l op-code, mode-add mrs illegal
k4x51323pc - 7(8)e/g march 2006 20 mobile-ddr sdram functional truth table current state cs ras cas we address command action write l h h l x burst stop illegal l h l h ba, ca, a10 read/reada terminate burst with dm=high, latch ca, begin read, determine auto-precharge *3 l h l l ba, ca, a10 write/writea terminate burst, latch ca, begin new write, determine auto-pre- charge *3 l l h h ba, ra active bank active/illegal *2 l l h l ba, a10 pre/prea terminate burst with dm=high, precharge l l l h x refresh illegal llllop-code, mode-addmrs illegal read with auto precharge *6 (reada) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada *6 l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active *6 llhl ba, a10 pre/prea *6 l l l h x refresh illegal llllop-code, mode-addmrs illegal write with auto recharge *7 (writea) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada *7 l h l l ba, ca, a10 write/writea *7 l l h h ba, ra active *7 l l h l ba, a10 pre/prea *7 l l l h x refresh illegal llllop-code, mode-addmrs illegal
k4x51323pc - 7(8)e/g march 2006 21 mobile-ddr sdram functional truth table current state cs ras cas we address command action precharging (during trp) l h h l x burst stop illegal *2 l h l x ba, ca, a10 read/write illegal *2 l l h h ba, ra active illegal *2 l l h l ba, a10 pre/prea nop *4 (idle after trp) lllhx refresh illegal l l l l op-code, mode-add mrs illegal row activating (from row active to trcd) l h h l x burst stop illegal *2 l h l x ba, ca, a10 read/write illegal *2 l l h h ba, ra active illegal *2 llhl ba, a10 pre/prea illegal *2 lllhx refresh illegal l l l l op-code, mode-add mrs illegal write recovering (during twr or tcdlr) l h h l x burst stop illegal *2 l h l h ba, ca, a10 read illegal *2 l h l l ba, ca, a10 write write l l h h ba, ra active illegal *2 l l h l ba, a10 pre/prea illegal *2 lllhx refresh illegal l l l l op-code, mode-add mrs illegal
k4x51323pc - 7(8)e/g march 2006 22 mobile-ddr sdram functional truth table current state cs ras cas we address command action re- freshing l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal l l h l ba, a10 pre/prea illegal l l l h x refresh illegal llllop-code, mode-add mrs illegal mode register setting l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal llhl ba, a10 pre/prea illegal l l l h x refresh illegal llllop-code, mode-add mrs illegal
k4x51323pc - 7(8)e/g march 2006 23 mobile-ddr sdram functional truth table abbreviations : h=high level, l=low level, x=don t care note : 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of that bank. (illegal = device oper- ation and/or data integrity are not guaranteed.) 3. must satisfy bus contention, bus turn around and write recovery requirements. 4. nop to bank precharging or in idle sate. may precharge bank indicated by ba. 5. illegal if any bank is not idle. 6. refer to "read with auto precharge timing diagram" for detailed information. 7. refer to "write with auto precharge timing diagram" for detailed information. 8. cke low to high transition will re-enable ck, ck and other inputs asynchronously. a minimum setup time must be satisfied before issuing any com- mand other than exit. 9. power-down, self-refresh and deep power down mode can be entered only from all bank idle state. 10. the deep power down mode is exited by asserting cke high and full initialization is required after exiting deep power down mode. current state cke n-1 cke n cs ras cas we add action self- refreshing *8 l h h x x x x exit self-refresh l h l h h h x exit self-refresh lhlhhlxillegal lhlhlxxillegal l h l l x x x illegal l l x x x x x noperation(maintain self-refresh) power down l h x x x x x exit power down(idle after tpdex) l l x x x x x noperation(maintain power down) deep power down lh hxxxx exit deep power down *10 l l x x x x x noperation(maintain deep power down) all banks idle*9 h h x x x x x refer to function true table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x enter deep power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state=power down any state other than listed above h h x x x x x refer to function truth table

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